A data transmission system for implementing data transmission/reception among electronic circuits in a computer exists. FIG. 13 is a block diagram which illustrates electronic circuits in a general computer.
A computer 50 illustrated in FIG. 13 is disposed while plural electronic circuits 50A are mounted therein. The computer 50 contains, as the plural electronic circuits 50A, plural input/output units 51 for inputting/outputting various kinds of data, plural memories 52 for storing various kinds of data, CPUs 53 for controlling various kinds of programs, a crossbar switch 54 which connects plural input/output units 51 to dynamically select a transmission route for data, and north bridges 55 for controlling data transmission among the memories 52, CPUs 53 and the crossbar switch 54.
For example, CPU 53 and the north bridge 55, the north bridge 55 and the crossbar switch 54, and the input/output unit 51 and the crossbar switch 54 are respectively connected to each other through data transmission lines, and data transmission/reception is implemented through the data transmission lines.
However, in order to enhance the performance of the computer, it is important to mutually increase the speed of data transmission between electronic circuits, that is, between a data transmission device and a data reception device. In order to increase the speed of the data transmission, the transmission waveform is deteriorated due to signal reflection or transmission loss, and it has been required to implement data transmission under an environment having a very severe margin.
In order to implement high-speed data transmission, retraining processing has become popular as a technique of adjusting and setting circuit control parameters of a data transmission device and a data reception device to optimum values in accordance with the environment.
Therefore, there is known a data transmission system having a retraining function of adjusting and setting the circuit control parameters of the data reception device in accordance with the environment so as to implement high-speed data transmission between electronic circuits, that is, between the data transmission device and the data reception device. FIG. 14 is a block diagram showing the schematic internal construction of a data transmission system as described above.
The data transmission system 100 shown in FIG. 14 has a data transmission device 102 for transmitting data, a data reception device 103 for receiving data from the data transmission device 102, and a data transmission line 104 through which the data transmission device 102 and the data reception device 103 are connected.
Next, the operation of the data transmission system 100 will be described.
When detecting a retraining signal, the data transmission device 102 starts to execute the retraining processing, reads out a fixed test pattern stored in the data transmission device 102, and transmits the read-out fixed test pattern through a data transmission line 104A to the data reception device 103.
When receiving the fixed test pattern from the data transmission device 102, the data reception device 103 reads out a collation pattern which is stored in the data reception device 103 and corresponds to the received fixed test pattern.
Then, the data reception device 103 collates the fixed test pattern received from the data transmission device 102 with the collation pattern stored in the data reception device 103.
When the fixed test pattern is coincident with the collation pattern, it is determined that the circuit parameter of the data reception device 103 is an optimum value, and the retraining processing is finished.
When the fixed test pattern is not coincident with the collation pattern, the circuit parameter is adjusted and set so that the fixed test pattern and the collation pattern are coincident with each other to set the circuit parameter of the data reception device 103 to the optimum value, whereby the circuit parameter of the data reception device 103 is set to the optimum value.    [Patent Document] JP-A-5-167679    [Patent Document] JP-A-2006-50102
However, in the data transmission system 100, the fixed test pattern and the collation pattern corresponding to the fixed test pattern which are used in the retraining processing are predetermined fixed patterns. When the test pattern and the collation pattern are not a test pattern and a collation pattern which are suitable for a system environment temperature at which the data transmission system is in operation and a device production variation, it is difficult to adjust and set the circuit parameter of the optimum data reception device which is adaptive to the system environment temperature and the device production variation.
An object of the present invention is to implement a system environment suitable for high-speed data transmission by using re-transmission data under operation as a test pattern and a collation pattern and adjusting and setting a circuit parameter of an optimum data reception device which is adaptive to a system environment temperature under operation and a device production variation.